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Espressif Systems /ESP32-S2 /RTC_CNTL /SLOW_CLK_CONF

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Interpret as SLOW_CLK_CONF

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (ANA_CLK_DIV_VLD)ANA_CLK_DIV_VLD 0ANA_CLK_DIV0 (SLOW_CLK_NEXT_EDGE)SLOW_CLK_NEXT_EDGE

Description

RTC slow clock configuration register

Fields

ANA_CLK_DIV_VLD

Synchronizes the reg_rtc_ana_clk_div bus. Note that you have to invalidate the bus before switching clock, and validate the new clock.
ANA_CLK_DIV

Set the rtc_clk divider.
SLOW_CLK_NEXT_EDGE

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data